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ispLSI 2064V
3.3V High Density Programmable Logic Features
* HIGH DENSITY PROGRAMMABLE LOGIC -- 2000 PLD Gates -- 64 and 32 I/O Pin Versions, Four Dedicated Inputs -- 64 Registers -- High Speed Global Interconnect -- Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. -- Small Logic Block Size for Random Logic 3.3V LOW VOLTAGE 2064 ARCHITECTURE -- Interfaces with Standard 5V TTL Devices -- The 64 I/O Pin Version is Fuse Map Compatible with 5V ispLSI 2064 HIGH-PERFORMANCE E2CMOS(R) TECHNOLOGY -- fmax = 100MHz Maximum Operating Frequency -- tpd = 7.5ns Propagation Delay -- Electrically Erasable and Reprogrammable -- Non-Volatile -- 100% Tested at Time of Manufacture -- Unused Product Term Shutdown Saves Power IN-SYSTEM PROGRAMMABLE -- 3.3V In-System Programmability (ISPTM) Using Boundary Scan Test Access Port (TAP) -- Open-Drain Output Option for Flexible Bus Interface Capability, Allowing Easy Implementation of Wired-OR or Bus Arbitration Logic -- Increased Manufacturing Yields, Reduced Time-toMarket and Improved Product Quality -- Reprogram Soldered Devices for Faster Prototyping THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAs -- Enhanced Pin Locking Capability -- Three Dedicated Clock Input Pins -- Synchronous and Asynchronous Clocks -- Programmable Output Slew Rate Control -- Flexible Pin Placement -- Optimized Global Routing Pool Provides Global Interconnectivity
Input Bus
(R)
Functional Block Diagram
Output Routing Pool (ORP)
A0
Output Routing Pool (ORP)
*
Input Bus
A2
GLB
Logic Array
DQ
DQ
B1
D
DQ
*
A3 A4 A5
B0
A7
EW
A6
Output Routing Pool (ORP)
Input Bus
N
*
0139A/2064V
SI
20
64
*
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* ispDesignEXPERTTM - LOGIC COMPILER AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING -- Superior Quality of Results -- Tightly Integrated with Leading CAE Vendor Tools -- Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZERTM -- PC and UNIX Platforms
Copyright (c) 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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The ispLSI 2064V is a High Density Programmable Logic Device available in 64 and 32 I/O-pin versions. The device contains 64 Registers, four Dedicated Input pins, three Dedicated Clock Input pins, two dedicated Global OE input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 2064V features in-system programmability through the Boundary Scan Test Access Port (TAP). The ispLSI 2064V offers non-volatile reprogrammability of the logic, as well as the interconnect, to provide truly reconfigurable systems. The basic unit of logic on the ispLSI 2064V device is the Generic Logic Block (GLB). The GLBs are labeled A0, A1...B7 (see Figure 1). There are a total of 16 GLBs in the ispLSI 2064V device. Each GLB is made up of four macrocells. Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any GLB on the device.
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Description
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
September 2000
2064v_10
1
Input Bus
A1
DQ
B2
Output Routing Pool (ORP)
Global Routing Pool (GRP)
ES IG N
B3
S
B7
B6
B5
B4
Specifications ispLSI 2064V
Functional Block Diagram
Figure 1. ispLSI 2064V Functional Block Diagram (64-I/O and 32-I/O Versions)
GOE 0
GOE 1
I/O 63 I/O 62 I/O 61 I/O 60
I/O 59
I/O 58 I/O 57
I/O 56
I/O 55 I/O 54 I/O 53 I/O 52
I/O 51 I/O 50 I/O 49 I/O 48
I/O 31 I/O 30 I/O 29 I/O 28
Input Bus
Generic Logic Blocks (GLBs)
I/O 27 I/O 26 I/O 25 I/O 24
Input Bus
Megablock
B7
Output Routing Pool (ORP)
B6 B5 B4
Megablock
B7
Output Routing Pool (ORP)
B6 B5 B4
Output Routing Pool (ORP)
Output Routing Pool (ORP)
Output Routing Pool (ORP)
Input Bus
Input Bus
Input Bus
I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 TDI/IN 0 TMS/IN 1
A2
B1
I/O 39 I/O 38 I/O 37 I/O 36 I/O 35 I/O 34 I/O 33 I/O 32 TCK/IN 3 TDO/IN 2
I/O 4 I/O 5 I/O 6 I/O 7 TDI/IN 0 TDO/IN 1
A2
D
A4 A5 A6 A7
B1
Input Bus
I/O 4 I/O 5 I/O 6 I/O 7
A1
Global Routing Pool (GRP)
B2
I/O 43 I/O 42 I/O 41 I/O 40
A1
Global Routing Pool (GRP)
B2
Output Routing Pool (ORP)
I/O 0 I/O 1 I/O 2 I/O 3
I/O 47
ES IG N
B3 B0
A0
B3
I/O 46 I/O 45 I/O 44
I/O 0 I/O 1 I/O 2 I/O 3
A0
A3
B0
A3
EW
A4
A5
A6
A7
CLK 0 CLK 1 CLK 2
ispEN
Input Bus
ispEN
Input Bus
Y0 Y1 Y2
I/O 8
I/O 9 I/O 10 I/O 11
I/O 12 I/O 13 I/O 14 I/O 15
The GRP has as its inputs, the outputs from all of the GLBs and all of the inputs from the bi-directional I/O cells. All of these signals are made available to the inputs of the GLBs. Delays through the GRP have been equalized to minimize timing skew. Clocks in the ispLSI 2064V device are selected using the dedicated clock pins. Three dedicated clock pins (Y0, Y1,
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Eight GLBs, 32 or 16 I/O cells, two dedicated inputs and two or one ORPs are connected together to make a Megablock (see Figure 1). The outputs of the eight GLBs are connected to a set of 32 or 16 universal I/O cells by two or one ORPs. Each ispLSI 2064V device contains two Megablocks.
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The 64-I/O 2064V contains 64 I/O cells, while the 32-I/O version contains 32 I/O cells. Each I/O cell is directly connected to an I/O pin and can be individually programmed to be a combinatorial input, output or bi-directional I/O pin with 3-state control. The signal levels are TTL compatible voltages and the output drivers can source 4 mA or sink 8 mA. Each output can be programmed independently for fast or slow output slew rate to minimize overall output switching noise. Device pins can be safely driven to 5-Volt signal levels to support mixed-voltage systems.
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64
20
FO
Y2) or an asynchronous clock can be selected on a GLB basis. The asynchronous or Product Term clock can be generated in any GLB for its own clock.
Programmable Open-Drain Outputs
In addition to the standard output configuration, the outputs of the ispLSI 2064V are individually programmable, either as a standard totem-pole output or an open-drain output. The totem-pole output drives the specified Voh and Vol levels, whereas the open-drain output drives only the specified Vol. The Voh level on the open-drain output depends on the external loading and pull-up. This output configuration is controlled by a programmable fuse. When this fuse is erased (JEDEC "1"), the output is configured as a totem-pole output. When this fuse is programmed (JEDEC "0"), the output is configured as an open-drain. The default configuration when the device is in bulk erased state is totem-pole configuration. The open-drain/totem-pole option is selectable through the ispDesignEXPERT software tools.
2
GOE1/Y0 RESET/Y1 TCK/Y2
0139B/2064V
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I/O 16 I/O 17
I/O 18 I/O 19
I/O 20 I/O 21 I/O 22 I/O 23
I/O 24 I/O 25 I/O 26 I/O 27
I/O 28 I/O 29 I/O 30 I/O 31
CLK 0 CLK 1 CLK 2
RESET
N
Output Routing Pool (ORP)
Output Routing Pool (ORP)
S
I/O 23 I/O 22 I/O 21 I/O 20 I/O 19 I/O 18 I/O 17 I/O 16 GOE0/IN 3 TMS/IN 2
0139B/2064V.32IO
Generic Logic Blocks (GLBs)
Specifications ispLSI 2064V
Absolute Maximum Ratings 1
Supply Voltage Vcc ................................................... -0.5 to +5.6V Input Voltage Applied ..................................... -0.5 to +5.6V Off-State Output Voltage Applied .................. -0.5 to +5.6V
Case Temp. with Power Applied .................... -55 to 125C Max. Junction Temp. (TJ) with Power Applied ............ 150C
1. Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications).
SYMBOL
PARAMETER Supply Voltage Input Low Voltage Input High Voltage Commercial Industrial
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DC Recommended Operating Condition
D
MIN. 3.0 3.0 VSS - 0.5 2.0 MAX. 3.6 3.6 0.8 5.25 UNITS V V V V
Table 2-0005/2064V
VCC VIL VIH
TA = -40C to + 85C
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Capacitance (TA=25C, f=1.0 MHz)
SYMBOL
FO
R
N
TA = 0C to + 70C
PARAMETER Dedicated Input Capacitance I/O Capacitance
TYPICAL 10 10 13
UNITS pf pf pf
20
C1 C2 C3
64
Clock and Global Output Enable Capacitance
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Data Retention Specifications
PARAMETER MINIMUM 20 10000 MAXIMUM - - UNITS Years Cycles
Table 2-0008/2064V
Data Retention
ispLSI Erase/Reprogram Cycles
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3
ES IG N
TEST CONDITIONS VCC = 3.3V, VIN = 2.0V VCC = 3.3V, VI/O = 2.0V VCC = 3.3V, VY = 2.0V
Table 2-0006/2064V
S
Storage Temperature ..................................... -65 to 150C
Specifications ispLSI 2064V
Switching Test Conditions
Input Pulse Levels Input Rise and Fall Time 10% to 90% Input Timing Reference Levels Output Timing Reference Levels Output Load 3-state levels are measured 0.5V from steady-state active level. GND to 3.0V 1.5 ns 1.5V 1.5V See Figure 2
Table 2-0003/2064V
Figure 2. Test Load
+ 3.3V R1
Output Load Conditions (see Figure 2)
TEST CONDITION A B Active High Active Low Active High to Z at VOH -0.5V Active Low to Z at VOL +0.5V R1 316 316 316 R2 348 348 348 348 348 CL 35pF 35pF 35pF 5pF 5pF
D
MIN. - 2.4 - - - - - - -
*CL includes Test Fixture and Probe Capacitance.
0213A/2064V
Table 2-0004/2064V
DC Electrical Characteristics
SYMBOL PARAMETER Output Low Voltage Output High Voltage Input or I/O Low Leakage Current
Over Recommended Operating Conditions
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FO
R
N
C
EW
CONDITION
64
VOL VOH IIL IIH IIL-isp IIL-PU IOS1 ICC2, 4
IOL= 8 mA IOH = -4 mA 0V VIN VIL (Max.)
ES IG N
R2 C L*
TYP. - - - - - - - - 82
3
Device Output
MAX. UNITS 0.4 - -10 10 50 -150 -150 -100 - V V A A mA A A mA mA
20
Input or I/O High Leakage Current
(VCC - 0.2)V VIN VCC V VIN 5.25V CC 0V VIN VIL 0V VIN VIL VCC = 3.3V, VOUT = 0.5V VIL = 0.0V, VIH = 3.0V fCLOCK = 1 MHz
I/O Active Pull-Up Current
Output Short Circuit Current
Table 2-0007/2064V 1. One output at a time for a maximum duration of one second. VOUT = 0.5V was selected to avoid test problems by tester ground degradation. Characterized but not 100% tested. 2. Measured using four 16-bit counters. 3. Typical values are at VCC = 3.3V and TA= 25C. 4. Maximum I CC varies widely with specific device configuration and operating frequency. Refer to the Power Consumption section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate maximum ICC .
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Operating Power Supply Current
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ispEN Input Low Leakage Current
4
S
Test Point
Specifications ispLSI 2064V
External Timing Parameters
Over Recommended Operating Conditions
PARAMETER TEST 2 # COND. A A A - - - A - - - - A - B C B C - - 1 2 3 4 5 6 7 8 9
4
DESCRIPTION
1
-100 - -
3 1
-80 - - 80.0 64.5 100 7.0 - 10.0 15.0 - - - - - -
-60 15.0 20.0 - - - -
MIN. MAX. MIN. MAX. MIN. MAX. 7.5 12.0 - - - - 5.0 - - - - 6.3
UNITS ns ns MHz
tpd1 tpd2 fmax fmax (Ext.) fmax (Tog.) tsu1 tco1 th1 tsu2 tco2 th2 tr1 trw1 tptoeen tptoedis tgoeen tgoedis twh twl
1. 2. 3. 4.
Data Propagation Delay, 4PT Bypass, ORP Bypass Data Propagation Delay Clock Frequency with Internal Feedback Clock Frequency, Max. Toggle GLB Reg. Setup Time before Clock, 4 PT Bypass GLB Reg. Clock to Output Delay, ORP Bypass GLB Reg. Hold Time after Clock, 4 PT Bypass GLB Reg. Setup Time before Clock Clock Frequency with External Feedback ( tsu2 + tco1)
102 83.3 125 5.5 - 0.0 7.0 - 0.0 - - - - - 4.0 4.0 5.0
61.7 51.3 71.4 9.0 - 0.0 - 0.0 - 8.0 - - - - 7.0 7.0
ES IG N
6.5 - - - 14.0 - 15.0 15.0 10.0 10.0 - - 8.5 - - - 16.0 - 18.0 18.0 12.0 12.0 - - 11.0 - - 7.5 9.5 - - - -
0.0 9.0
10 GLB Reg. Clock to Output Delay 11 GLB Reg. Hold Time after Clock 12 Ext. Reset Pin to Output Delay 13 Ext. Reset Pulse Duration 14 Input to Output Enable 15 Input to Output Disable 16 Global OE Output Enable 17 Global OE Output Disable
D
0.0 7.0 5.0 5.0
EW
12.0 13.0 13.0 7.5 7.5 - -
N
R
FO
18 External Synchronous Clock Pulse Duration, High 19 External Synchronous Clock Pulse Duration, Low
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20
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Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock. Refer to Timing Model in this data sheet for further details. Standard 16-bit counter using GRP feedback. Reference Switching Test Conditions section.
Table 2-0030/2064V
5
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ns ns ns ns ns ns ns ns ns ns ns ns ns ns
MHz MHz
Specifications ispLSI 2064V
Internal Timing Parameters1
Over Recommended Operating Conditions
PARAMETER Inputs #
2
DESCRIPTION
-100
-80
-60
MIN. MAX. MIN. MAX. MIN. MAX. - - - - - - - - - 0.2 0.6 0.7 4.6 6.0 6.7 7.5 8.5 0.3 - - 1.5 2.2 3.8 7.2 4.4 1.4 0.1 1.9 11.9 4.9 4.9 2.6 1.5 1.5 6.5 - - - 0.4 1.3 - - 0.6
UNITS
GRP
tgrp
GLB
22 GRP Delay 23 4 Product Term Bypass Path Delay (Combinatorial) 24 4 Product Term Bypass Path Delay (Registered) 25 1 Product Term/XOR Path Delay 26 20 Product Term/XOR Path Delay 27 XOR Adjacent Path Delay
3
ES IG N
1.2 - 2.1 5.8 7.5 9.2 9.5 11.3 0.3 - - 1.6 2.5 5.6 8.5 5.6 1.4 0.4 2.2 12.2 4.9 4.9 5.1 2.3 2.3 7.9 - - - - - - 0.2 8.0 - - - - 6.5 - - - - - - - 4.2 4.2 - 9.6 10.3 12.3 12.3 14.4 1.3 - - 1.6 2.8 9.3 10.4 9.3 1.5 0.5 2.2 12.2 4.9 4.9 7.1 4.2 4.2 9.5
tio tdin
21 Dedicated Input Delay
1.4
35 GLB Product Term Clock Delay 36 ORP Delay 37 ORP Bypass Delay
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t4ptbpc t4ptbpr t1ptxor t20ptxor txoradj tgbp tgsu tgh tgco tgro tptre tptoe tptck
ORP
- - - - - -
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0.2 5.4 - - - - 3.8 - - - - - - - 2.3 2.3 -
EW
28 GLB Register Bypass Delay 29 GLB Register Setup Time befor Clock 30 GLB Register Hold Time after Clock 31 GLB Register Clock to Output Delay 32 GLB Register Reset to Output Delay 33 GLB Product Term Reset to Register Delay
N
0.1 3.8 - - - - 3.0 - - - - - - - 1.5 1.5 -
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FO
34 GLB Product Term Output Enable to I/O Cell Delay
64
torp torpbp
Outputs
42 Global Output Enable
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tob tsl toen todis tgoe
Clocks
38 Output Buffer Delay
20
40 I/O Cell OE to Output Enabled 41 I/O Cell OE to Output Disabled
SI
39 Output Slew Limited Delay Adder
Global Reset
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tgr
SE
tgy0 tgy1/2
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43 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) 44 Clock Delay, Y1 or Y2 to Global GLB Clock Line 45 Global Reset to GLB
1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR adjacent path can only be used by hard macros.
Table 2-0036/2064V
6
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ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
20 Input Buffer Delay
ns
Specifications ispLSI 2064V
ispLSI 2064V Timing Model
I/O Cell GRP Feedback Ded. In Comb 4 PT Bypass #23 GLB ORP I/O Cell
#21 I/O Delay #20 GRP #22
20 PT XOR Delays #25, 26, 27 Reset #45 D
GLB Reg Delay Q #29, 30, 31, 32 RST
Y0,1,2 GOE 0,1
#43, 44 #42
N
EW
Control RE PTs OE #33, 34, CK 35
D
#40, 41
0491/2064
tsu
4.6 ns
th
0.7 ns
tco
10.1 ns
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Note: Calculations are based on timing specifications for the ispLSI 2064V-100L.
Table 2-0042/2064V
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= = = =
Clock (max) + Reg co + Output (tio + tgrp + tptck(max)) + (tgco) + (torp + tob) (#20 + #22 + #35) + (#31) + (#36 + #38) (0.2 + 0.7 + 4.4) + (1.5) + (1.4 + 1.9)
20
64
= = = =
Clock (max) + Reg h - Logic (tio + tgrp + tptck(max)) + (tgh) - (tio + tgrp + t20ptxor) (#20 + #22 + #35) + (#30) - (#20 + #22 + #26) (0.2 + 0.7 + 4.4) + (3.8) - (0.2 + 0.7 + 7.5)
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= = = =
Logic + Reg su - Clock (min) (tio + tgrp + t20ptxor) + (tgsu) - (tio + tgrp + tptck(min)) (#20 + #22 + #26) + (#29) - (#20 + #22 + #35) (0.2 + 0.7 + 7.5) + (0.1) - (0.2 + 0.7 + 3.0)
FO
Derivations of tsu, th and tco from the Product Term Clock
7
R
1
ES IG N
ORP Delay #36
I/O Pin (Input)
#24
#28
#37
S
Reg 4 PT Bypass
GLB Reg Bypass
ORP Bypass
#38, 39
I/O Pin (Output)
Specifications ispLSI 2064V
Power Consumption
Power consumption in the ispLSI 2064V device depends on two primary factors: the speed at which the device is operating and the number of Product Terms used. Figure 3. Typical Device Power Consumption vs fmax
120 ispLSI 2064V 110 100
Figure 3 shows the relationship between power and operating speed.
ICC (mA)
80 70
fmax (MHz)
ICC can be estimated for the ispLSI 2064V using the following equation: ICC(mA) = 10 + (# of PTs * 0.556) + (# of nets * Max freq * 0.0053) Where: # of PTs = Number of Product Terms used in design # of nets = Number of Signals used in device Max freq = Highest Clock Frequency to the device (in MHz) The ICC estimate is based on typical conditions (VCC = 3.3V, room temperature) and an assumption of two GLB loads on average exists. These values are for estimates only. Since the value of ICC is sensitive to operating conditions and the program in the device, the actual ICC should be verified.
20
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Notes: Configuration of Four 16-bit Counters Typical Current at 3.3V, 25 C
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0
25
50
75
EW
100
D
0127/2064
90
When Lattice 3.3-Volt 2000V devices are used in mixed 5V/3.3V applications, some consideration needs to be given to the power-up sequence. When the I/O pins on the 3.3V ispLSI devices are driven directly by 5V devices, a low impedance path can exist on the 3.3V device between its I/O and Vcc pins when the 3.3V supply is not present. This low impedance path can cause current to flow from the 5V device into the 3.3V ispLSI device. The maximum current occurs when the signals on the I/O pins are driven high by the 5V devices. If a large enough current flows through the 3.3V I/O pins, latch-up can occur and permanent device damage may result.
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Power-up Considerations
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This latch-up condition occurs only during the power-up sequence when the 5V supply comes up before the 3.3V supply. The Lattice 3.3V ispLSI devices are guaranteed to withstand 5V interface signals within the device operating Vcc range of 3.0V to 3.6V. The recommended power-up options are as follows: Option 1: Ensure that the 3.3V supply is powered-up and stable before the 5V supply is powered up. Option 2: Ensure that the 5V device outputs are driven to a high impedance or logic low state during power-up.
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8
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Specifications ispLSI 2064V
Pin Description
84-PIN PLCC PIN NUMBERS
26, 30, 34, 38, 45, 49, 53, 57, 68, 72, 76, 80, 3, 7, 11, 15 64, 19, 20 24 27, 31, 35, 39, 46, 50, 54, 58, 69, 73, 77, 81, 4 8, 12, 16, 22 67, 62 28, 32, 36, 40, 47, 51, 55, 59, 70, 74, 78, 82, 5, 9, 13, 17, 29, 33, 37, 41, 48, 52, 56, 60, 71, 75, 79, 83, 6, 10, 14, 18
NAME
I/O 0 - I/O 3 I/O 4 - I/O 7 I/O 8 - I/O 11 I/O 12 - I/O 15 I/O 16 - I/O 19 I/O 20 - I/O 23 I/O 24 - I/O 27 I/O 28 - I/O 31 I/O 32 - I/O 35 I/O 36 - I/O 39 I/O 40 - I/O 43 I/O 44 - I/O 47 I/O 48 - I/O 51 I/O 52 - I/O 55 I/O 56 - I/O 59 I/O 60 - I/O 63 GOE 0, GOE 1 Y0, Y1, Y2 RESET ispEN
100-PIN TQFP PIN NUMBERS
17, 22, 27, 32, 40, 45, 49, 55, 67, 72, 77, 82, 90, 95, 99, 5, 62, 10, 11 15 18, 23, 28, 33, 41, 46, 51, 56, 68, 73, 78, 83, 91, 96, 1, 6, 13 65, 60 19, 24, 29, 34, 42, 47, 52, 57, 69, 74, 79, 84, 92, 97, 2, 7,
DESCRIPTION
20, Input/Output Pins -- These are the general purpose I/O pins 26, used by the logic array. 30, 35, 43, 48, 53, 58, 70, 76, 80, 85, 93, 98, 3 8 Global Output Enable Input Pins
Dedicated Clock input. This clock input is connected to one of the clock inputs of all the GLBs in the device.
TDI/IN 0
25
16
VE
TMS/IN 1
43
37
64
TDO/IN 2
1
87
20
TCK/IN 3
61
59
VCC NC1
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GND
23, 2,
SI
44, 21,
63, 42,
84 65
14, 12, 4, 31, 54, 75, 100
39, 36, 9, 38, 64, 81
61, 63, 21, 44, 66, 88,
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66
SE
FO
Input -- This pin performs two functions. When ispEN is logic low, it functions as an input pin to load programming data into the device. TDI/IN 0 also is used as one of the two control pins for the ISP state machine. When ispEN is high, it functions as a dedicated input pin. Input -- This pin performs two functions. When ispEN is logic low, it functions as a pin to control the operation of the ISP state machine. When ispEN is high, it functions as a dedicated input pin. Output/Input -- This pin performs two functions. When ispEN is logic low, it functions as an output pin to read serial shift register data. When ispEN is high, it functions as a dedicated input pin. Input -- This pin performs two functions. When ispEN is logic low, it functions as a clock pin for the Serial Shift Register. When ispEN is high, it functions as a dedicated input pin.
86 89
Ground (GND) Vcc
25, No Connect. 50, 71, 94,
Table 2-0002A/2064V
1. NC pins are not to be connected to any active signals, VCC or GND.
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9
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Input -- Dedicated in-system programming enable input pin. This pin is brought low to enable the programming mode. The TMS, TDI, TDO and TCK controls become active.
N
Active Low (0) Reset pin which resets all registers in the device.
EW
D
ES IG N
S
Specifications ispLSI 2064V
Pin Description
44-PIN PLCC PIN NUMBERS
15, 19, 25, 29, 37, 41, 3, 7, 2 11 16, 20, 26, 30, 38, 42, 4, 8, 17, 21, 27, 31, 39, 43, 5, 9, 18, 22, 28, 32, 40, 44, 6, 10
NAME
I/O 0 - I/O 3 I/O 4 - I/O 7 I/O 8 - I/O 11 I/O 12 - I/O 15 I/O 16 - I/O 19 I/O 20 - I/O 23 I/O 24 - I/O 27 I/O 28 - I/O 31 GOE 0/IN 3 GOE 1/Y0
44-PIN TQFP PIN NUMBERS
9, 13, 19, 23, 31, 35, 41, 1, 40 5 10, 14, 20, 24, 32, 36, 42, 2, 11, 15, 21, 25, 33, 37, 43, 3, 12, 16, 22, 26, 34, 38, 44, 4
DESCRIPTION
Input/Output Pins -- These are the general purpose I/O pins used by the logic array.
This pin performs one of two functions. It can be programmed to function as a Global Output Enable pin or a Dedicted Input pin. This pin performs one of two functions. It can be programmed to function as a Global Output Enable or a Dedicated Clock input. This clock input is connected to one of the clock inputs of all the GLBs on the device.
RESET/Y1
35
29
ispEN
13
7
VE
TMS/IN 2
36
30
64
TDO/IN 1
24
18
20
TCK/Y2
33
27
pL
SI
GND VCC
1,
23 34
17, 6,
39 28
is
12,
FO
TDI/IN 0
14
8
R
Input -- Dedicated in-system programming enable input pin. This pin is brought low to enable the programming mode. The TMS, TDI, TDO and TCK controls become active.
Input -- This pin performs two functions. When ispEN is logic low, it functions as an input pin to load programming data into the device. TDI/IN 0 also is used as one of the two control pins for the ISP state machine. When ispEN is high, it functions as a dedicated input pin.
Input -- This pin performs two functions. When ispEN is logic low, it functions as a pin to control the operation of the ISP state machine. When ispEN is high, it functions as a dedicated input pin. Output/Input -- This pin performs two functions. When ispEN is logic low, it functions as an output pin to read serial shift register data. When ispEN is high, it functions as a dedicated input pin. Input -- This pin performs two functions. When ispEN is logic low, it functions as a clock pin for the Serial Shift Register. When ispEN is high, it functions as a dedicated clock input. This clock input is brought into the Clock Distribution Network, and can optionally be routed to any GLB and/or I/O cell on the device. Ground (GND) Vcc
Table 2-0002B/2064V
U
SE
10
N
EW
This pin performs one of two functions. It can be programmed to function as a Dedicated Clock Input that is brought into the Clock Distribution Network and can optionally be routed to any GLB and/or I/O cell on the device, or as an Active Low (0) Reset pin which resets all of the GLB and I/O registers in the device.
D
ES IG N
S
Specifications ispLSI 2064V
Pin Configuration
ispLSI 2064V 100-Pin TQFP Pinout Diagram
NC1 I/O 56 I/O 55 I/O 54 I/O 53 I/O 52 NC1 I/O 51 I/O 50 I/O 49 I/O 48 VCC NC1 TDO/IN 2 GND I/O 47 I/O 46 I/O 45 I/O 44 NC1 I/O 43 I/O 42 I/O 41 I/O 40 I/O 39
pL
I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 1NC I/O 12 I/O 13 I/O 14 I/O 15 VCC TMS/IN 1 1NC GND I/O 16 I/O 17 I/O 18 I/O 19 1NC I/O 20 I/O 21 I/O 22 I/O 23 I/O 24 1NC
SI
20
I/O 57 I/O 58 I/O 59 1NC I/O 60 I/O 61 I/O 62 I/O 63 1NC Y0 RESET VCC GOE 1 GND ispEN TDI/IN 0 I/O 0 I/O 1 I/O 2 I/O 3 1NC I/O 4 I/O 5 I/O 6 1NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
Top View
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
64
VE
FO
R
N
ispLSI 2064V
EW
D
11
1. NC pins are not to be connected to any active signals, VCC or GND.
U
SE
is
ES IG N
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 NC1 I/O 38 I/O 37 I/O 36 NC1 I/O 35 I/O 34 I/O 33 I/O 32 NC1 Y1 NC1 VCC GOE 0 GND Y2 TCK/IN 3 I/O 31 I/O 30 I/O 29 I/O 28 NC1 I/O 27 I/O 26 I/O 25
100 TQFP/2064V
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
S
Specifications ispLSI 2064V
Pin Configuration
ispLSI 2064V 84-Pin PLCC Pinout Diagram I/O 48 VCC TDO/IN 2
I/O 56
I/O 55 I/O 54
I/O 53
I/O 52 I/O 51 I/O 50 I/O 49
I/O 47
I/O 46
I/O 45
I/O 44
I/O 43
I/O 42
I/O 41 I/O 40 I/O 39
GND
I/O 57 I/O 58 I/O 59 I/O 60 I/O 61 I/O 62 I/O 63 Y0 RESET VCC GOE 1 GND ispEN TDI/IN 0 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6
12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
D EW N FO
ispLSI 2064V
Top View
R
VE
64
20
SI
is
pL
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
I/O 11 I/O 12 I/O 13 I/O 14 I/O 16 VCC TMS/IN 1 I/O 19 I/O 20 I/O 15 GND I/O 17 I/O 18 I/O 10 I/O 21 I/O 22 I/O 23 I/O 24 I/O 7 I/O 8 I/O 9
U
SE
1. NC pins are not to be connected to any active signal, VCC or GND.
12
ES IG N
74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54
84 PLCC/2064V
11 10 9
8
7
6
5
4
3
2
1 84 83 82 81 80 79 78 77 76 75
I/O 38 I/O 37 I/O 36 I/O 35 I/O 34 I/O 33 I/O 32 Y1 NC1 VCC GOE 0 GND
Y2 TCK/IN 3 I/O 31 I/O 30 I/O 29 I/O 28 I/O 27 I/O 26 I/O 25
S
Specifications ispLSI 2064V
Pin Configuration
GOE 0/IN 3
ispLSI 2064V 44-Pin PLCC Pinout Diagram
I/O 27 I/O 26 I/O 25 I/O 24
I/O 23
I/O 22
I/O 29 I/O 30 I/O 31 GOE1/Y0 VCC ispEN TDI/IN 0 I/O 0 I/O 1 I/O 2
38 37 36 35 34 33 32 31 30 29
I/O 17 I/O 16 TMS/IN 2
9 10 11 12 13 14 15 16 17
ispLSI 2064V
Top View
RESET/Y1 VCC TCK/Y2 I/O 15 I/O 14 I/O 13 I/O 12
18 19 20 21 22 23 24 25 26 27 28
GND
I/O 3
I/O 4 I/O 5
I/O 6
I/O 7
I/O 8
TDO/IN 1
R
I/O 9 I/O 10 I/O 11
N
ispLSI 2064V 44-Pin TQFP Pinout Diagram
I/O 27
GOE 0/IN 3
I/O 26 I/O 25
64
I/O 24
VE
Pin Configuration
GND I/O 23
I/O 22
FO
20
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 I/O 18 I/O 17 I/O 16 TMS/IN 2 RESET/Y1 VCC TCK/Y2 I/O 15 I/O 14 I/O 13 I/O 12
SI
I/O 28 I/O 29 I/O 30 I/O 31
pL
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
GND TDO/IN 1 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 I/O 11
is
GOE1/Y0 VCC ispEN TDI/IN 0 I/O 0 I/O 1 I/O 2
I/O 21 I/O 20 I/O 19
ispLSI 2064V
Top View
SE
U
13
EW
44 PLCC/2064V
29 28 27 26 25 24 23
44 TQFP/2064V
D
ES IG N
I/O 28
7 8
39
I/O 18
S
6 5 4 3 2 1 44 43 42 41 40
I/O 21 I/O 20 I/O 19
GND
Specifications ispLSI 2064V
Part Number Description
ispLSI
Device Family Device Number Speed 100 = 100 MHz fmax 80 = 80 MHz fmax 60 = 60 MHz fmax
2064V - XXX X
XXX X
Grade Blank = Commercial I = Industrial
D
COMMERCIAL
FAMILY fmax (MHz) 100 100 100 100 80 ispLSI 80 80 80 60 60 60 60 tpd (ns) 7.5 7.5 7.5 7.5 10 10 10 10 15 15 15 I/Os 64 64 32 32 64 64 32 32 64
N
ORDERING NUMBER
EW
ispLSI 2064V Ordering Information
ispLSI 2064V-100LJ84 ispLSI 2064V-100LJ44 ispLSI 2064V-80LJ84 ispLSI 2064V-80LJ44 ispLSI 2064V-80LT44 ispLSI 2064V-60LJ84 ispLSI 2064V-60LT100 ispLSI 2064V-60LJ44 ispLSI 2064V-60LT44
R
ispLSI 2064V-100LT100
FO
ispLSI 2064V-100LT44 ispLSI 2064V-80LT100
VE
64
20
64 32 32
15
SI
FAMILY ispLSI
fmax (MHz)
pL
INDUSTRIAL
I/Os 64 32 ORDERING NUMBER ispLSI 2064V-60LT100I ispLSI 2064V-60LT44I PACKAGE 100-Pin TQFP 44-Pin TQFP
Table 2-0041B/2064V
tpd (ns) 15 15
U
SE
is
60 60
14
ES IG N
0212/2064V
Package T100 = 100-Pin TQFP J84 = 84-Pin PLCC J44 = 44-Pin PLCC T44 = 44-Pin TQFP Power L = Low
PACKAGE 84-Pin PLCC 100-Pin TQFP 44-Pin PLCC 44-Pin TQFP 84-Pin PLCC 100-Pin TQFP 44-Pin PLCC 44-Pin TQFP 84-Pin PLCC 100-Pin TQFP 44-Pin PLCC 44-Pin TQFP
Table 2-0041A/2064V
S

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